Very strict PCB design delivery checklist

2019 08/22

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Very strict PCB design delivery checklist
Data input stage			1	Is the data received on the process complete (including schematic diagram,*.brd file, material list, PCB design specification and PCB design or change requirements, standardization requirements specification, process design specification document)
			2	Verify that the PCB template is up to date
			3	Verify that the position of the positioning device of the template is correct
			4	Whether the PCB design instructions and PCB design or change requirements, standardization requirements are clear or not
			5	Verify that the forbidden placement devices and wiring areas on the contour map are reflected on the PCB template.
			6	Compare the outline drawings to confirm that the dimensions and tolerances indicated by PCB are correct, and the definitions of metallized and non-metallized holes are accurate.
			7	After confirming that the PCB template is correct, it is better to lock the structure file in order to avoid misoperation being moved.
Post-Layout Inspection Phase	Device Inspection		8	Verify that all device packages are correct.
			9	Motherboard and daughterboard, veneer and backboard, confirm signal correspondence, position correspondence, connector direction and screen mark correct, and daughterboard has anti-error insertion measures, daughterboard and device on motherboard should not interfere.
			10	Are components 100% positioned?
			11	Open the Place-bound of TOP and BOTTOM layers to see if DRC caused by overlap is allowed
			12	Is Mark Point Adequate and Necessary
			13	Heavier components should be placed near PCB support points or support edges to reduce warpage of PCB.
			14	Structurally related devices should be locked after they are well laid to prevent misoperation and moving position.
			15	Within the 5 mm range around the pressure socket, no elements with height higher than the height of the pressure socket are allowed on the front side, and no elements or solder joints are allowed on the back side.
			16	Confirm whether the device layout meets the process requirements (focus on BGA, PLCC, patch socket)
			17	For the components of metal shell, special attention should be paid not to collide with other components, but to leave enough space for them.
			18	Interface-related devices should be placed as close as possible to the interface, and backplane bus drivers should be placed as close as possible to the backplane connector.
			19	Have CHIP devices on wave soldering surfaces been converted into wave soldering packages?
			20	Is there more than 50 manual solder joints?
			21	Horizontal installation should be considered when installing higher components axially on PCB. Leave room for sleeping. And consider the fixing mode, such as the fixed pad of crystal oscillator.
			22	It is necessary to use radiator devices to ensure that there is sufficient distance from other devices, and pay attention to the height of the main devices within the radiator range.
	Functional examination		23	Whether the layout of digital circuit and analog circuit components of digital-analog hybrid board has been separated and whether the signal flow is reasonable
			24	A/D converters are placed across analog-to-digital partitions.
			25	Whether the layout of clock devices is reasonable
			26	Reasonable Layout of High Speed Signal Devices
			27	Are End-connected Devices Reasonably Placed
				(The source matched series resistance should be placed in the driver of the signal; the intermediate matched series resistance should be placed in the middle; and the terminal matched series resistance should be placed in the receiver of the signal.)
			28	Whether the number and position of decoupling capacitors of IC devices are reasonable
			29	The reference plane of the signal line is the plane of different levels. Whether the connecting capacitance between the reference planes is close to the line area of the signal when crossing the plane partition area.
			30	Whether the layout of protection circuit is reasonable or not, and whether it is conducive to segmentation
			31	Whether the fuse of the veneer power supply is located near the connector without any circuit elements in front of it
			32	Confirm that the strong signal and the weak signal (power difference 30 dB) circuits are separated
			33	Whether to place devices that may affect EMC experiments according to design guidelines or referring to successful experience. For example, the reset circuit of the panel should be slightly closer to the reset button.
	Heat management		34	Thermal sensitive components (including liquid dielectric capacitors, crystal oscillators) should be as far away from high-power components, radiators and other heat sources as possible.
	Heat management		35	Whether the layout satisfies the thermal design requirements, heat dissipation channels (according to process design documents)
	Power Supply		36	Whether IC power supply is too far from IC
			37	Is LDO and Circuit Arrangement Reasonable
			38	Are the Circuits Around Modular Power Supply Reasonable
			39	Is the overall layout of power supply reasonable?
	Rule Settings		40	Whether all simulation constraints have been correctly added to Constraint Manager
			41	Whether the physical and electrical rules are set correctly (pay attention to the constraints of power and ground networks)
			42	Testing, testing
			43	Does the thickness and scheme of the laminates meet the design and processing requirements?
			44	Whether all differential line impedances with characteristic impedance requirements have been calculated and controlled by rules
Post-wiring Inspection Phase	Mathematical model		45	Are the routes of digital and analog circuits separated and the signal flow reasonable?
			46	If A/D, D/A and similar circuits are separated, does the signal line between the circuits go up from the bridge point between the two places (except the differential line)?
			47	Signal lines that must span the gap between the dividing power sources should refer to the complete horizon.
			48	If the stratum design zoning is not divided, the zoning wiring of digital and analog signals should be ensured.
	Clock and High Speed Section		49	Whether the impedance layers of high-speed signal lines are consistent
			50	Are high-speed differential signal lines and similar signal lines aligned equally, symmetrically and nearly parallel?
			51	Make sure that the clock line is as deep as possible
			52	Verify that clock lines, high-speed lines, reset lines and other strong radiation or sensitive lines have been routed as far as possible according to the 3W principle
			53	Are there no bifurcated test points on clocks, interrupts, reset signals, 100 mega/gigabit Ethernet and high-speed signals?
			54	Does 10H (H is the height of signal line distance reference plane) be satisfied between low level signals such as LVDS and TTL/CMOS signals as far as possible?
			55	Do clock lines and high-speed signal lines avoid traversing dense through-hole through-hole areas or inter-pin wiring of devices?
			56	Whether the clock line has met the (SI constraint) requirement
				(Whether the routing of clock signal should be less perforated, shorter and continuous, the main reference plane should be GND as far as possible;
				If the main reference plane layer of GND is changed when the layer is changed, the GND through hole is in the range of 200 mil from the through hole.
				If the main reference planes of different levels are changed during layer replacement, is there a decoupling capacitance within 200 mil of the through hole?
			57	Differential pairs, high-speed signal lines and various BUS have met the requirements of (SI constraint)
	EMC and Reliability		58	For crystal oscillator, is there a layer under it? Does it avoid the signal line crossing between the pins of the device? For high-speed sensitive devices, does it avoid the signal line crossing between the pins of the devices?
			59	There should be no sharp angle and right angle on the single board signal line (generally turning at 135 degrees, the RF signal line should be arced or calculated corner-cutting copper foil).
			60	For double sided PCB, check whether the high-speed signal line is closely connected with its return ground line; for multi-layer panels, check whether the high-speed signal line is as close as possible to the ground line.
			61	For adjacent two-layer signal routing, try to go vertically as far as possible
			62	Avoid signal line from power supply module, common-mode inductance, transformer, filter down-crossing
			63	Avoid long-distance parallel traveling of high-speed signals on the same layer as far as possible
			64	Are there any shielded holes on the edges of the plate, which are digital, analog and protected? Are multiple horizons connected by via holes? Is the distance through holes less than 1/20 of the maximum frequency signal wavelength?
			65	Is the signal path corresponding to the surge suppression device short and thick on the surface?
			66	Confirm that there are no islands in the power supply, no excessive grooves, no long ground fissures, no slender strips and narrow channels caused by excessive or dense through-hole isolation disks.
			67	Are ground crossings (at least two ground planes required) placed where signal lines cross more layers?
	Power supply and ground		68	If the power/ground plane is divided, try to avoid the spanning of high-speed signals on the separated reference plane.
			69	Confirm that the power supply and ground can carry enough current. Whether the number of through holes meets the load-bearing requirements
			69	(Estimation method: 1 A/mm linewidth at 1 oz outer copper thickness, 0.5 A/mm inner linewidth and double short current)
			70	For power supply with special requirements, whether it meets the requirement of voltage drop or not
			71	In order to reduce the radiation effect at the edge of the plane, the 20H principle should be satisfied as far as possible between the power layer and the stratum.
			71	(If conditions permit, the more indented the power supply layer, the better.)
			72	If the existing land is divided, does the divided land not constitute a loop?
			73	Does the overlapping placement of different power supply planes in adjacent layers be avoided?
			74	Are the isolation of protected sites, - 48V sites and GND greater than 2mm?
			75	- Are the 48V sites only - 48V signal reflux and not connected to other locations? If you can't do it, please explain the reason in the remarks column.
			76	Are 10 to 20 mm protective sites located near the connector panel and connected with each layer by double-row staggered holes?
			77	Is the distance between the power line and other signal lines meeting the safety requirements?
	Closed area		78	It is not possible to cause short-circuit wiring, copper skin and through-hole under metal shell devices and heat dissipation devices.
			79	Installation of screw or gasket around should not be possible to cause short-circuit wiring, copper skin and through holes; screw holes in accordance with the design of star-moon holes; the surrounding forbidden distance to meet more than 20 mil
			80	Are the reserved positions in the design requirements aligned?
			81	The distance between inner layer separation circuit and copper foil in non-metallic hole should be greater than 0.5 mm (20 mil) and 0.3 mm (12 mil) in outer layer.
			81	The distance between inner layer separation line and copper foil in axle hole of veneer pull-out wrench should be more than 2 mm (80 mil)
			82	Copper sheet and wire to edge recommended for more than 2 mm minimum 0.5 mm
			83	Copper skin in inner stratum to edge of plate 1-2 mm, minimum 0.5 mm
	Welding Pad Outgoing Line		84	For CHIP components installed on two pads (0805 and below), such as resistors and capacitors, the printed wire connected with the pad should be drawn symmetrically from the central position of the pad, and the printed wire connected with the pad must have the same width. This requirement may not be taken into account for the lead wire whose width is less than 0.3mm (12mil).
			84	The pad connected with a wider printed line is preferably transited through a narrow printed line. (0805 and below package)
			86	Circuit should be drawn from both ends of solder pad of SOIC, PLCC, QFP, SOT and other devices as far as possible.
	Silk screen printing		87	Whether the device position number is missing and whether the position can correctly identify the device
			88	Whether the device bit number is named accurately or not, and whether it meets the requirements according to the classification
			89	Verify the order of pins, the first pin, the polarity of the device, and the correctness of the direction of the connector.
			90	Does the orientation mark of the insert of the motherboard and the daughterboard correspond to each other?
			91	Whether the backplane correctly identifies the slot name, slot number, port name, sheath direction
			92	Verify the correctness of the silk print addition required by the design
			93	Verify that anti-static and radio frequency board identification has been placed (radio frequency board used)
	Coding/Barcode		94	Confirm that the PCB code is correct and set the PCB code specification according to the company's situation.
			95	Verify that the PCB coding position and level of the veneer are correct (should be in the upper left of side A, screen printing layer)
			96	Verify that the PCB coding position and level of the backplane are correct (should be in the upper right of B, outer copper foil)
			97	Confirmation of white screen marking area with bar code laser printing
			98	Verify that there is no connection under the bar code frame and no through hole larger than 0.5mm
			99	Verify that no components with a height exceeding 25 mm are allowed in the 20 mm range outside the white screen printing area of the bar code.
	Through hole		100	On the reflow surface, the through hole can not be designed on the pad. (The spacing between pass and pad of normal window opening should be greater than 0.5mm (20mil), and between pass and pad covered with green oil should be greater than 0.1mm (4mil). Method: Open Same Net DRC, check DRC, and then close Same Net DRC.
			101	The arrangement of through holes should not be too close to avoid large-scale breakage of power supply and ground surface.
			102	The borehole diameter should be no less than 1/10 of the plate thickness.
103			Whether the device placement rate is 100%, whether the placement rate is 100%(not up to 100% needs to be explained in the notes)
104			Whether the Dangling line has been adjusted to a minimum or not has been confirmed one by one for the retained Dangling line.
105			Has the process problem feedback from the process department been carefully checked?
Large area copper foil	106		For large area copper foil on Top and Bottom, if there is no special need, grid copper is applied [inclined net for veneer, orthogonal net for backplane, line width 0.3 mm (12 mil) and spacing 0.5 mm (20 mil)]
	107		Component pads in large area of copper foil area should be designed as flower pads to avoid virtual welding. When there is a current requirement, the reinforcement of flower pads should be widened first, and then the full connection should be considered.
	108		When copper is widely distributed, the dead copper without network connection should be avoided as far as possible.
	109		Large area copper foil should also pay attention to whether there is illegal connection, unreported DRC
Test points	110		Whether the test points of various power supply and ground are adequate (at least one test point per 2A current)
	111		Verify that networks without test points are validated and streamlined
	112		Verify that no test points are set on plug-ins that are not installed at production time
	113		Test Via, Test Pin whether Fix (suitable for testing needle bed invariable change board)
DRC Optical Location Point	114		The interval rule of test via and test pin should be set to the recommended distance to check drc. If DRC still exists, then check DRC with the minimum distance setting.
	115		Open Constraints Set to Open State, Update DRC, See if there are any inadmissible errors in DRC
	116		Confirm that DRC has been adjusted to a minimum, and confirm that DRC can not be eliminated one by one.
	117		Confirm that optical positioning symbols exist on PCB surfaces with mounting elements
	118		Confirmation of Unembossed Optical Positioning Symbols (Screen Printing and Copper Foil Routing)
	119		The background of the optical positioning point should be the same. Make sure that the whole board uses the optical point whose center is more than 5 mm away from the edge.
	120		It is confirmed that the optical positioning reference symbols of the whole board have been assigned coordinate values (it is suggested that the optical positioning reference symbols should be placed in the form of devices) and be an integral value in millimeters.
	121		For IC with pin center distance less than 0.5 mm and BGA devices with center distance less than 0.8 mm (31 mil), optical positioning points should be set near the diagonal of the components.
Weld Resistance Inspection	122		Verify that all pads with special requirements are properly windowed (especially hardware design requirements)
	123		Whether the through hole under BGA is treated as capping plug hole or not
	124		Have small windows or oil plug holes been made in addition to test holes
	125		Does the window opening of optical positioning point avoid exposure of copper and exposed wire?
	126		Power chips, crystal oscillators and other devices requiring copper skin heat dissipation or ground shielding, whether there is copper skin and correctly open windows. Devices fixed by solder should have green oil to block large-scale diffusion of solder
Making Processing Documents	Borehole Map	127		Notes'PCB thickness, number of layers, screen printing color, warpage, and other technical specifications are correct
		128		Whether the layer name, stacking sequence, dielectric thickness and copper foil thickness of the laminate are correct, whether impedance control is required, and whether the description is accurate. Does the Layer Name of the Overlay Diagram coincide with its Light Drawing File Name?
		129		Turn off the Repeat code in the Settings table and set the drilling accuracy to 2-5.
		130		Are hole lists and drilling documents up to date (when changing holes, they must be regenerated)
		131		Whether there is abnormal aperture in the pore table, whether the aperture of the press joint is correct, whether the aperture tolerance is correctly marked.
		132		Are the through holes of the fortress holes listed separately and marked "filled vias"
	Light painting	133		RS274X format should be adopted as far as possible in the output of light drawing files, and the accuracy should be set to 5:5.
		134		Is art_aper.txt up to date (274X is not required)
		135		Is there an exception report in the log file of the output light drawing file?
		136		Margin of Negative Layer and Isolation Confirmation
		137		Check whether the photo-drawing files are in accordance with PCB by using the photo-drawing inspection tool (the comparison tool should be used to compare the change boards)
A complete set of documents	138			PCB Document: Product Model Specification Veneer Code Version Number. BRD
	139			Backplane Lining Design Document: Product Model Specification Veneer Code Version Number - CB [-T/B]. BRD
	140			PCB Processing Documents: PCB Code. zip (including all layers of light drawing documents, diaphragm table, drilling documents and ncdrill. log; jigsaw also needs jigsaw documents *. DXF provided by the process)
	140			The backplane also has lining files: PCB encoding - CB [- T/B]. zip (including drill. art, *. drl, ncdrill. log)
	141			Process Design Document: Product Model Specification Veneer Code Version Number - GY. doc
	142			SMT coordinate file: product model specification veneer code version number - SMT. TXT
	142			(When outputting coordinate files, confirm the selection of Body Center. Symbol origin can only be selected when confirming that the origin of all SMD device libraries is device center.)
	143			PCB board structure file: product model specification veneer code version number - MCAD. zip (including. DXF and. EMN files provided by structural engineers)
	144			Test file: Product model specification veneer code version number - TEST. ZIP (including coordinate files of testprep. log and untest. LST or *. DRL test points)
	145			Archived Drawing Documents: Product Model Specification - Veneer Name - Version Number. pdf
	145			(Including: cover, home page, screen printing of each layer, line of each layer, borehole drawing, backplane with lining plate drawing)
Standardization	146			Verify that the cover and home page information is correct
	147			Verify that the drawing serial number (corresponding to PCB layers in sequence) is correct

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