How to deal with signal reflection in the design of high-speed PCB board
In high-speed PCB boards, routing is more than just connecting two points. As a qualified engineer, routing is a hybrid knowledge carrier including resistance, capacitance and inductance. Signal lines will reflect in the transmission process, which must be understood that the size of reflection at the load side depends on the Z of the transmission line and the Z of the load.
The reflection coefficient of the signal is measured by the reflection coefficient KR, which is KRL= (ZL-Z0)/(ZL+Z0) at the load end, KRL=1 for the open-circuit load, KRL=-1 for the short-circuit load, and 100% for the open-circuit load and the short-circuit load. The negative value of KRL indicates that the reflected signal is opposite to the original signal. Similarly, the magnitude of signal reflection at the source is expressed by the reflection coefficient at the source: KRS= (ZS-Z0)/(ZS+Z0).
If the standard output level of the driver is 0.2V and the current is 24mA, the output impedance ZS is about 8.3. If the input impedance ZL of the load is greater than 100K and much larger than Z0 (about 67), the reflection coefficient of the load end is KRL=1, and the signal is reflected by 100% at the load end. The source reflection coefficient is KRS=-0.78.
The following is a detailed analysis of the driver's reflection process from 3.5V to 0.2V signal.
First reflection: The driver voltage is 3.3V. According to the principle of voltage dividing between ZS and Z0, the signal generated on Z0 is Delta V=-2.94V, and the source signal voltage is VS=O.56V. The reflection coefficient at the load end is 1. When the signal reaches the load end, VL = 3.5-2.94-2.94=-2.38V.
Second reflection: The starting source signal is 0.56V. When the - 2.94V signal arrives at the source, the second reflection occurs. The reflection voltage is VR = KPS* Delta V = - 0.78* (- 2.94) = 2.29V. So the source voltage becomes VS=0.56+(-2.94)+2.29=-0.09V.
Third reflection: When the second reflection signal reaches the load terminal, the voltage at the load terminal becomes VL =-2.38+2.29+2.29=2.2.V.
In this impedance mismatched transmission line, the signal is reflected back and forth in this way, and the amplitude of each reflection decreases a little until it finally disappears. The vertical lines on the left and right represent the voltage at the source and load ends respectively, while the oblique lines indicate the voltage of the transmitted signal and the reflected signal. It can also be used to represent the specific reflection process of the signal, one for the source signal and one for the load signal. It can be seen that after five cycles, the signal transmitted to the load side will fall below the input threshold. The transmission delay is generally between 6-16ns/m. If the transmission delay tPD = 10ns/m, the delay through a 0.15m transmission line is about 1.5ns, then the signal can be considered as having a transmission delay of about 13.5ns. Effective.
