100 Notices in PCB Design
1. Is the data received on the process complete (including schematic diagram, BRD file, material list, PCB design specification and PCB design or change requirements, standardization requirements specification, process design specification document)
2. Confirm that the PCB template is up-to-date.
3. Verify that the position of the positioning device of the template is correct.
4. Whether the PCB design instructions and PCB design or change requirements and standardization requirements are clear or not.
5. Verify that the prohibited placement devices and wiring areas on the contour map are already reflected on the PCB template.
6. Compare the outline drawings to confirm that the dimensions and tolerances indicated by PCB are correct, and the definitions of metallized and non-metallized holes are accurate.
7. After confirming that the PCB template is correct, it is better to lock the structure file in order to avoid misoperation being moved.
8. Verify that all device packages are consistent with the company's unified library, whether the package library has been updated (check the running results with viewlog) If not, be sure to Update Symbols.
9. Motherboard and daughterboard, veneer and backboard, confirm signal correspondence, position correspondence, correct direction of connector and screen marking, and daughterboard has anti-misinsertion measures, daughterboard and device on motherboard should not interfere.
10. Are components 100% placed?
11. Open the Place-bound of TOP and BOTTOM layers to see if DRC caused by overlap is allowed.
12. Is Mark Point Adequate and Necessary.
13. Heavier components should be placed near the PCB support point or support edge to reduce the warpage of PCB.
14. Structurally related devices should be locked to prevent misoperation and movement.
15. Within the 5 mm range around the press socket, no elements with a height higher than the height of the press socket are allowed on the front side, and no elements or solder joints are allowed on the back side.
16. Verify whether the device layout meets the process requirements (focus on BGA, PLCC, patch socket).
17. Special attention should be paid to the components of metal shells, not to touch other components, and to leave enough space for them.
18. Place the interface-related devices as close as possible to the interface, and the backplane bus driver as close as possible to the backplane connector.
19. Has CHIP device on wave soldering surface been converted into wave soldering package?
20. Is there more than 50 manual solder joints?
21. Horizontal installation should be considered when axially inserting higher components on PCB. Leave room for sleeping. And consider the fixing mode, such as the fixed pad of crystal oscillator.
22. Devices requiring radiators should be identified to be sufficiently spaced from other devices, and attention should be paid to the height of the main components within the radiator range.
23. Whether the digital circuit and analog circuit components of digital-analog hybrid board have been separated and whether the signal flow is reasonable.
24. Placement of A/D Converter across A/D Partitions.
25. Belonging to Qinji Group, Baineng Network is a leading service platform for the electronic industry in China. It provides a complete set of solutions for the supply chain of electronic industry, such as components online, sensor purchasing, PCB customization, BOM allocation, material selection and so on. It meets the overall needs of small and medium-sized customers in the electronic industry one-stop.
26. Whether the layout of clock devices is reasonable.
27. Is the layout of high-speed signal devices reasonable?
28. Whether the terminal device has been reasonably placed (the source matched series resistance should be placed at the driver end of the signal; the intermediate matched series resistance should be placed at the intermediate position; and the terminal matched series resistance should be placed at the receiver end of the signal).
29. Is the number and position of decoupling capacitors of IC devices reasonable?
30. Signal lines use different level planes as reference planes. Whether the connecting capacitance between reference planes is close to the line area of the signal when crossing the plane partition area.
31. Is the layout of protection circuit reasonable and conducive to segmentation?
32. Does the fuse of the veneer power supply lie near the connector without any circuit elements in front of it?
33. Verify that the strong signal and the weak signal (power difference 30 dB) circuits are separated.
34. Whether to place devices that may affect EMC experiments according to design guidelines or referring to successful experience. For example, the reset circuit of the panel should be slightly closer to the reset button.
35. Thermal sensitive components (including liquid dielectric capacitors, crystal oscillators) should be as far away from high-power components, radiators and other heat sources as possible.
36. Whether the layout satisfies the thermal design requirements and the heat dissipation channel (according to the process design documents).
37. Whether all simulation constraints have been correctly added to Constraint Manager.
38. Whether the physical and electrical rules are set correctly (pay attention to the constraints of power and ground networks).
39. Is the spacing of Test Via and Test Pin adequate?
40. Does the thickness and scheme of the laminates meet the design and processing requirements?
41. Whether all differential line impedances with characteristic impedance requirements have been calculated and controlled by rules.
42. Is the routing of digital and analog circuits separated and the signal flow reasonable?
43, If A/D, D/A and similar circuits are separated, does the signal line between the circuits go from the bridge point between the two places (with the exception of the differential line).
44. Signal lines that must span the gap between dividing power sources should refer to the complete horizon.
45. If stratigraphic design zoning is adopted, the zoning wiring of digital and analog signals should be ensured.
46. Is IC power supply too far from IC?
47. Is LDO and Circuit Layout Reasonable.
48. Are the Circuit Layout Around Modular Power Supply Reasonable.
49. Is the overall layout of power supply reasonable?
50. Are high-speed differential signal lines and similar signal lines aligned equally, symmetrically and nearly parallel?
51. Make sure that the clock line is inside as far as possible.
52. Verify that clock lines, high-speed lines, reset lines and other strong radiation or sensitive lines have been routed according to 3W principle as far as possible.
53, Clock, Interrupt, Reset Signal, 100M/Gigabit Ethernet, High Speed Signal whether there is no Bifurcation Test Point.
54. Whether the low-level signals, LVDS and TTL/CMOS signal can meet 10 as far as possible.
55. Does the clock line and the high-speed signal line avoid traversing the dense through-hole area or the pin-to-pin routing of the device?
56. Whether the clock line has met the requirement of SI constraint (whether the clock signal routing should be less perforated, shorter and continuous, the main reference plane should be GND as far as possible; if the main reference plane layer of GND is changed when changing the layer, the main reference level of GND is changed when changing the layer, and within the range of 200 mil from the hole), if the layer is changed, the main reference level of GND is changed. Plane, whether there is decoupling capacitance within the range of 200 mil from the hole).
57. Differential pairs, high-speed signal lines and various BUS have met (SI constraints) requirements.
58. For crystal oscillator, is there a layer under it? Does it avoid the signal line crossing between the pins of the device? For high-speed sensitive devices, is it possible to avoid the crossing of signal lines from the pins of devices?
59. There should be no sharp and right angles on the signal line of the veneer (generally turning at 135 degrees, the radio frequency signal line should be circular arc or corner-cutting copper foil after calculation).
60. For double sided PCB, check whether the high-speed signal line is closely connected with its return ground line; for multi-layer PCB, check whether the high-speed signal line is as close as possible to the ground line.
61. For adjacent two-layer signal routing, try to go vertically.
62. Avoid signal line from power supply module, common-mode inductance, transformer, filter down-crossing.
63. Avoid long-distance parallel traveling of high-speed signals on the same layer as far as possible.
64. Are there any shielded holes on the edges of the plate and the dividing edges of the digital, analog and protected areas? Are multiple horizons connected by via holes? Is the distance through holes less than 1/20 of the maximum frequency signal wavelength?
65. Is the signal routing corresponding to the surge suppression device short and thick on the surface?
66. Confirm that there are no islands, grooves, long ground fissures, slender strips and narrow passages caused by too large or dense through-hole isolation disks in power supply, strata.
67. Are ground crossing holes (at least two ground planes required) placed in places where signal lines cross more layers?
68. If the power/ground plane is divided, try to avoid the spanning of high-speed signals on the separated reference plane.
69. Confirm that the power supply and ground can carry enough current. Whether the number of through holes meets the load-carrying requirements (estimation method: 1 A/mm linewidth at 1 oz outer copper thickness, 0.5 A/mm linewidth at inner copper thickness, double short current).
70. For power supply with special requirements, whether it meets the requirements of voltage drop.
71. In order to reduce the edge radiation effect of the plane, the 20H principle should be satisfied as far as possible between the power layer and the stratum. (If conditions permit, the more indented the power supply layer, the better).
72. If the existing land is partitioned, does the partitioned land not constitute a loop?
73. Does the overlapping placement of different power supply planes in adjacent layers be avoided?
74. Whether the isolation of protective site, -48V site and GND is greater than 2mm.
75. - 48V sites only a signal return of - 48V and not connected to other locations? If you can't do it, please explain the reason in the remarks column.
76. Are 10-20 mm protective sites located near the panel with connectors, and the layers are connected by two rows of staggered holes?
77. Whether the distance between the power line and other signal lines meets the safety requirements.
78. For CHIP components installed on two pads (0805 and packages below), such as resistors and capacitors, the printed wire connected with the pad should be drawn symmetrically from the central position of the pad, and the printed wire connected with the pad must have the same width. This provision may not be taken into account for the lead wire whose width is less than 0.3mm (12mil).
79. Welding pads connected with wider printed lines are best transited through a narrow printed line in the middle. (0805 and below package).
80. Circuit should be drawn from the two ends of solder pad of SOIC, PLCC, QFP, SOT and other devices as far as possible.
81. It is not possible to cause short-circuit wiring, copper skin and through-hole under metal shell devices and heat dissipation devices.
82. Installation of screw or gasket around should not cause short-circuit wiring, copper skin and through-hole.
83. Are the reserved positions in the design requirements aligned?
84. The distance between inner layer separation line and copper foil in non-metallic hole should be greater than 0.5 mm (20 mil) and 0.3 mm (12 mil) in outer layer. The distance between inner layer separation line and copper foil in axle hole of single board pull-out wrench should be greater than 2 mm (80 mil).
85. Copper sheet and wire to edge are recommended to be greater than 2 mm and the minimum is 0.5 mm.
86. Copper skin in inner stratum to edge of plate 1-2 mm, minimum 0.5 mm.
87. Belonging to Qinji Group, Baineng Network is a leading service platform for the electronic industry in China. It provides a complete set of solutions for the supply chain of electronic industry, such as components online, sensor purchasing, PCB customization, BOM allocation, material selection and so on. It meets the overall needs of small and medium-sized customers in the electronic industry one-stop.
88. Verify that the PCB code is correct and conforms to company specifications.
89. Verify that the PCB coding position and level of the veneer are correct (should be in the upper left of side A, screen printing layer).
90. Verify that the PCB coding position and level of the backplane are correct (should be in the upper right of B, the outer copper foil surface).
91. Confirmation of white silk screen marking area with bar code laser printing.
92. Confirm that there is no connection under the bar code frame and no through hole larger than 0.5mm.
93. Verify that no components with a height exceeding 25 mm can be found in the 20 mm range outside the white screen printing area of barcode.
94. Whether the device bit number is missing and whether the position can correctly identify the device.
95. Does the device number meet the company's standards?
96. Verify the order of pins, the first pin, the polarity of the device, and the correctness of the direction of the connector.
97. Does the orientation mark of the insert of the motherboard and the daughterboard correspond to each other?
98. Whether the backplane correctly identifies the slot name, slot number, port name and sheath direction.
99. Verify the correctness of the silk print addition required by the design.
100. Verify that anti-static and radio frequency board identification has been placed (radio frequency board used).
